1. Field of the Invention
The present invention relates to the field of computer memory architecture and, more particularly, to cache memories used in conjunction with Static Random Access Memories (SRAM) to improve overall performance.
2. Description of the Background
The central processing unit (CPU) of a computer typically operates at a much faster speed than the access time of the memory to which the CPU is connected. The problem is exacerbated by the fact that memory arrays having a high density, which typically makes them less expensive then memory arrays having a lower density, are often slower than memory arrays which have a lower density. Thus, there is always a trade off between speed and cost.
To help ameliorate the effects of that trade off, computer designers use both types of memory. The relatively slower memory, which is inexpensive, is used to provide the vast bulk of the memory required and is referred to as the main memory. The more expensive, faster memory, is provided as a buffer between the CPU and the main memory, and is referred to as cache memory.
Studies have been conducted to identify the information stored in the main memory which should also be stored in the cache memory. Obviously, the more often the CPU can find the information that it needs in the cache memory, rather than having to go to the slower main memory, the faster the CPU can operate. Sophisticated algorithms have been developed to determine what information should be maintained in the cache memory and what information should be overwritten when new information is to be stored.
It is known to organize cache memory according to certain mapping techniques. For example, see U.S. Pat. No. 5,367,653 which is entitled Reconfigurable Multi-Associative Cache Memory. One type of mapping is referred as direct mapping. In that mapping scheme, a main memory address is divided into two fields, an index field comprised of the least significant bits of an address and a tag field comprised of the remaining significant bits of the address. The entire address, i.e., the tag field and the index field, is needed to access the main memory, while only the index field is needed to access the cache memory. The remainder of the address, i.e., the tag field, is stored in the tag memory, sometimes referred to as a tag cache. In operation, the index field from an address for a requested piece of data is input to the tag cache, and the tag associated with that address is output. If the tag output from the tag cache matches the tag field of the requested data, then a hit results indicating that the requested data is in the data cache. If there is a miss, the data must be retrieved from the main memory.
Other types of mapping techniques are also known. For example, in fully associative mapping, the cache memory stores both the main memory address and the data word thus allowing a word from main memory to be stored in any location in the cache memory. For example, if a fifteen-bit main memory address is located in an argument register, and the contents of the argument register are compared with the main memory addresses stored in associative cache memory, a hit results when the contents of the argument register equals one of the main memory addresses stored in cache memory.
Another type of mapping, referred to as set-associative mapping, permits the storage of two or more words in cache memory at the same index address. The data words stored in the cache memory at the same index are each associated with a tag. The number of tag/word pairs stored at one address forms a "set". A cache memory which has multiple cache words at one cache address is referred to as a multi-way cache. Thus, a cache memory which provides for two words to be stored under a single address is referred to as a two-way cache. A cache memory which stores four words under a single address is referred to as a four-way cache. Because the cache memory utilizes an associative mapping function, the cache memory may be referred to as a two-way, set associative cache or a four-way, set associative cache, respectively.
Different configurations of cache memory are used for different applications. For example, two-way set associative cache is often adequate for instruction whereas four-way set associative cache often provides better performance for data. The type of cache memory can be established by proper hardware selection if the particular use is known. If the particular use is not known, the reconfigurable multi-way associative cache memory disclosed in the aforementioned U.S. Pat. No. 5,367,653 may be used. However, there remains a need for a tag cache circuit which is sufficiently flexible to enable it to be easily modified so as to expand the number of ways. Such a circuit should provide the flexibility of a software configurable cache memory while at the same time providing the advantages provided by a hard-wired circuit.